A Process Technology for Fabricating Submicron Ballistic Electron Vertical Diodes for THz Frequency Power Generation

GaN ballistic or quasi-ballistic electron devices require short transit distances in the order of a mean free path to avoid longitudinal optical phonon LO emission. Vertical current flow by design takes full advantage of the abrupt and thin layers grown by molecular beam epitaxy (MBE). Moreover, crystal orientation becomes important when ballistic transport is involved since bandstructure depends on direction and ballistic devices utilize the portions of the conduction band where parabolic assumption does not hold. C-axis growth of GaN is very mature and produces very high quality crystals and for ballistic devices with vertical current flow, this offers a unambiguous known bandstructure. In this summary, our process development efforts for a ballistic diode for terahertz (THz) generation based on negative differential conductivity is presented [1-3]. Summary of Research: The process begins with the definition of the active mesa by a dry etch process (ICP) in chlorine based chemistry. A 100 nm thick carbon film was used as a hard mask due to its high selectivity with GaN and its inert nature. The carbon mask, due to its large grain size also needs patterning with another mask. The process sequence is: 1. Evaporate carbon on the chip without any mask. 2. Liftoff Cr using high resolution e-beam lithography. 3. Dry etch carbon in O2 plasma masked by Cr. 4. Wet etch Cr to prevent it from sputtering in low pressure, high power chlorine based chemistry. Figure 1: Mesa and lower level ohmic contact. Figure 2: Deposited Si3N4. Coverage is conformal. The lower level ohmic contact lift-off is done using e-beam lithography. Ohmic resistances are measured and recorded at this step. Then, a plasma enhanced chemical vapor deposition (PECVD) of 400-500 nm Si3N4 follows (higher than the mesa). This dielectric layer is deposited to be utilized in the planarization and passivation of the GaN surface. Before the high temperature ohmic anneal, the whole chip is taken through a stepped anneal process in